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CY2278A
Pentium/II Clock Synthesizer/Driver for Mobile PCs with Intel 82430TX and No SDRAM
Features
* Mixed 2.5V and 3.3V operation * Complete clock solution to meet requirements of mobile Pentium(R) and Pentium(R) II motherboards -- Seven CPU clock outputs (three at 3.3V, and four at 2.5V or 3.3V) with eight selectable clock frequencies. -- Ten 3.3V synchronous PCI clock outputs -- Two 3.3V USB/IR clocks at 48 MHz -- One Keyboard clock at 8 MHz -- One 2.5V IOAPIC clock at 14.318 MHz -- Two 3.3V Ref. clocks at 14.318 MHz * Dedicated power management for portable systems -- Separate output enable pins for CPU, PCI, and USB/IR clock sets -- Free-running PCI and CPU clocks (see options) * Factory-EPROM programmable output drive and slew rate for EMI customization * Custom configuration with factory-EPROM programmable CPU, PCI, and USB/IR frequencies. * Low skew and low jitter outputs * Available in space-saving 48-pin TSSOP package voltage applied on pin 42. There are ten PCI clocks, running at one half the CPU clock frequency. Free-running PCI and CPU clocks are available as options shown in the selector guide. Additionally, the part outputs two 3.3V USB/IR clocks at 48 MHz, one Keyboard clock at 8 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and two 3.3V reference clocks at 14.318 MHz. The CY2278 family contains several features for output flexibility and power control. The CPU, PCI, USB and IR clock frequencies are all factory EPROM-programmable. Three hardware select inputs support eight CPU clock frequencies from 20 - 75 MHz. Additionally, each of the CPU, PCI, and USB/IR clock sets can be turned on or off with a dedicated enable input pin for power management. The CY2278A outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control.
CY2278A Selector Guide
Clock Outputs CPU@3.3V CPU@2.5/3.3V PCI (CPU/2MHz) USB/IR (48MHz) KB (8MHz) IOAPIC (14.318 MHz) Ref (14.318MHz) CPU-PCI delay
Notes: 1. One free-running CPU clock. 2. Two free-running PCI clocks.
-1L 3 4[1] 10[2] 2 1 2 2 0 ns
-2L 3 4 10 2 1 2 2 0 ns
-3L 3 4 10[2] 2 1 2 2 1-5 ns
-4L 3 4 10[2] 2 1 2 2 0 ns
Functional Description
The CY2278A is a Clock Synthesizer/Driver chip for Pentium, or Pentium II portable PCs designed with the 82430TX or similar core-logic chipsets. There are four options available as shown in the selector guide. The CY2278A outputs seven CPU clocks, three of which run at 3.3V and four run at either 2.5V or 3.3V, depending on the
Logic Block Diagram
14.318 MHz
2.5-3.3V Driver IOAPIC REF[0-1]
48 MHz D CK /12 8 MHZ
XIN
XOUT
OSC.
96 MHz PLL0 D CK /2
USB_RUN
USBCLK/IRCLK
CLK8MHz 2.5-3.3V Driver XCPUCLK [0-2] XCPUCLK3_F on -1L only; not freerunning on -2L, -3L, -4L CPUCLK [0-2]
SEL2 SEL1 SEL0
EPROM
CPUCLK PLL1
CPU_RUN
D CK /2
D CK PCICLK
PCICLK [2-9] PCICLK_F [0-1] on -1L, -3L, -4L only; not freerunning on -2L
PCI_RUN
D CK
D CK
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 October 14, 1999
CY2278A
Pin Configurations
TSSOP Top View
REF1 REF0 VSS XIN XOUT VDDQ3 PCICLK0_F PCICLK1_F VSS PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDDQ3 PCICLK6 VSS PCICLK7 PCICLK8 VDDQ3 PCICLK9 CLK8MHz VDDQ3 USBCLK IRCLK 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 VDDQ2 IOAPIC PWR_DWN VSS XCPUCLK0 XCPUCLK1 VDDCPU XCPUCLK2 XCPUCLK3_F VSS CPUCLK0 CPUCLK1 VDDQ3 CPUCLK2 SEL0 VSS SEL1 VSS SEL2 CPU_RUN USB_RUN PCI_RUN AVDD VSS REF1 REF0 VSS XIN XOUT VDDQ3 PCICLK0 PCICLK1 VSS PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDDQ3 PCICLK6 VSS PCICLK7 PCICLK8 VDDQ3 PCICLK9 CLK8MHz VDDQ3 USBCLK IRCLK 1 2 3 4 5 6 7 8 9
TSSOP Top View
48 47 46 45 44 43 42 41 VDDQ2 IOAPIC PWR_DWN VSS XCPUCLK0 XCPUCLK1 VDDCPU XCPUCLK2 XCPUCLK3 VSS CPUCLK0 CPUCLK1 VDDQ3 CPUCLK2 SEL0 VSS SEL1 VSS SEL2 CPU_RUN USB_RUN PCI_RUN AVDD VSS
39 2278A-1L 11 38 37 36 35 34 33 32 31 30 29 28 27 26 25
40 10 39 2278A-2L 11 38 12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 32 31 30 29 28 27 26 25
TSSOP Top View
REF1 REF0 VSS XIN XOUT VDDQ3 PCICLK0_F PCICLK1_F VSS PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDDQ3 PCICLK6 VSS PCICLK7 PCICLK8 VDDQ3 PCICLK9 CLK8MHz VDDQ3 USBCLK IRCLK 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 VDDQ2 IOAPIC PWR_DWN VSS XCPUCLK0 XCPUCLK1 VDDCPU XCPUCLK2 XCPUCLK3 VSS CPUCLK0 CPUCLK1 VDDQ3 CPUCLK2 SEL0 VSS SEL1 VSS SEL2 CPU_RUN USB_RUN PCI_RUN AVDD VSS REF1 REF0 VSS XIN XOUT VDDQ3 PCICLK0_F PCICLK1_F VSS PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDDQ3 PCICLK6 VSS PCICLK7 PCICLK8 VDDQ3 PCICLK9 CLK8MHz VDDQ3 USBCLK IRCLK 1 2 3 4 5 6 7 8 9
TSSOP Top View
48 47 46 45 44 43 42 41 40 VDDQ2 IOAPIC PWR_DWN VSS XCPUCLK0 XCPUCLK1 VDDCPU XCPUCLK2 XCPUCLK3 VSS CPUCLK0 CPUCLK1 VDDQ3 CPUCLK2 SEL0 VSS SEL1 VSS SEL2 CPU_RUN USB_RUN PCI_RUN AVDD VSS
40 10 39 2278A-3L 38 11 12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 32 31 30 29 28 27 26 25
10 39 2278A-4L 38 11 12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 32 31 30 29 28 27 26 25
2
CY2278A
Pin Summary
Name VDDQ3 VDDQ2 VDDCPU AVDD VSS XTALIN SEL2 SEL1 SEL0 PCI_RUN USB_RUN CPU_RUN PWR_DWN XCPUCLK[0:2] XCPUCLK3_F CPUCLK[0:2] PCICLK[2:9] PCICLK_F[0:1] CLK8MHZ IOAPIC REF[0:1] USBCLK/IRCLK
[3] [3]
Pins 6, 14, 19, 22, 36 48 42 26 3, 9, 16, 25, 31, 33, 39, 45 4 5 30 32 34 27 28 29 46 44, 43, 41 40 38, 37, 35 7, 8 21 47 2, 1 23, 24
Description 3.3V Digital voltage supply IOAPIC Digital voltage supply, 2.5V CPU Digital voltage supply, 2.5V or 3.3V Analog voltage supply, 3.3V Ground Reference crystal input Reference crystal feedback CPU clock frequency select input, bit 2 CPU clock frequency select input, bit 1 CPU clock frequency select input, bit 0 Control input, stops all PCI clocks except PCICLK_F when driven LOW Control input, stops all USB/IR clocks when driven LOW Control input, stops all CPU clocks except XCPUCLK_F when driven LOW Power down input, shuts down device when driven LOW 2.5V or 3.3V CPU clock outputs 2.5V or 3.3V CPU clock output, free-running on CY2278A-1L only. This output is not free-running on the -2L, -3L, -4L configurations. 3.3V CPU clock output PCI clock outputs, free-running on CY2278A-1L, -3L, -4L only. This output is not free-running on the -2L configuration 8-MHz Keyboard clock output IOAPIC clock output Reference clock outputs, 14.318 MHz. REF0 has high drive USB or IR clock outputs, 48 MHz
XTALOUT
10, 11, 12, 13, 15, 17, 18, 20 PCI clock outputs
Note: 3. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Function Table
SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 XTALIN 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz CPUCLK 75.0 MHz 20.0 MHz 25 MHz 33.33 MHz 50.0 MHz 60.0 MHz 66.67 MHz 40.0 MHz PCICLK 37.5 MHz 10.0 MHz 12.5 MHz 16.67 MHz 25.0 MHz 30.0 MHz 33.33 MHz 20.0 MHz REF IOAPIC 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz USBCLK IRCLK 48.0 MHz 48.0 MHz 48.0 MHz 48.0 MHz 48.0 MHz 48.0 MHz 48.0 MHz 48.0 MHz CLK8MHZ 8.0 MHz 8.0 MHz 8.0 MHz 8.0 MHz 8.0 MHz 8.0 MHz 8.0 MHz 8.0 MHz
3
CY2278A
Actual Clock Frequency Values
Clock Output CPUCLK(0,0,0) CPUCLK(0,0,1) CPUCLK(0,1,0) CPUCLK(0,1,1) CPUCLK(1,0,0) CPUCLK(1,0,1) CPUCLK(1,1,0) CPUCLK(1,1,1) USBCLK[4] CLK8MHz Target Frequency (MHz) 75.0 MHz 20.0 MHz 25 MHz 33.33 MHz 50.0 MHz 60.0 MHz 66.67 MHz 40.0 MHz 48.0 8.0 75.0 19.979 24.974 33.298 49.947 60.0 66.654 39.992 48.008 8.001 Actual Frequency (MHz) 0 -1057 -1057 -1107 -1057 0 -171 -196 167 167 PPM
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5
Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Package Power Dissipation .............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[5]
Parameter AVDD, V DDQ3 VDDCPU, VDDQ2 TA CL Description Analog and Digital Supply Voltage CPU and IOAPIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on XCPUCLK, CPUCLK, USBCLK/IRCLK, CLK8MHZ, REF1, IOAPIC PCICLK REF0 Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 2.375 0 Max. 3.465 2.625 70 20 20 30 45 14.318 MHz Unit V V C pF
f(REF)
Notes: 4. Meets Intel USB clock requirements. 5. Electrical parameters are guaranteed with these operating conditions.
Electrical Characteristics
Parameter VIH VIL VOH VOL Description High-level Input Voltage Low-level Input Voltage Except Crystal Inputs[6] Except Crystal Inputs
[6]
Test Conditions
Min. Max. Unit 2.0 0.8 V V V 0.4 V
High-level Output Voltage VDDCPU, VDDQ2 = 2.375V Low-level Output Voltage VDDCPU, VDDQ2 = 2.375V
IOH = 9 mA
XCPUCLK
2.0
IOH = 13 mA IOAPIC IOL = 13 mA XCPUCLK IOL = 18 mA IOAPIC
4
CY2278A
Electrical Characteristics
Parameter VOH Description Test Conditions IOH = 23 mA XCPUCLK IOH = 23 mA CPUCLK IOH = 23 mA PCICLK IOH = 23 mA USBCLK IOH = 23 mA CLK8MHZ IOH = 23 mA REF0 IOH = 23 mA REF1 VOL Low-level Output Voltage VDDQ3, AVDD, VDDCPU = 3.135V IOL = 17 mA XCPUCLK IOL =17 mA CPUCLK IOL = 17 mA PCICLK IOL = 17 mA USBCLK IOL = 17 mA CLK8MHZ IOL = 17 mA REF0 IOL = 17 mA REF1 IIH IIL IDD IDD IDDS Input High Current Input Low Current Power Supply Current
[7]
Min. Max. Unit 2.4 V
High-level Output Voltage VDDQ3, AVDD, VDDCPU = 3.135V
0.4
V
VIH = V DD VIL = 0V VDDQ3 = 3.465V, V IN = 0 or VDD, Loaded Outputs, CPU clocks = 66.67 MHz VDDQ3 = 3.465V, V IN = 0 or VDD, Unloaded Outputs Current draw in power-down state
-10
+10 10 200 100 150
A A mA mA A
Power Supply Current[7] Power-down Current
Notes: 6. Crystal inputs have CMOS thresholds. 7. Power supply current will vary with number of outputs which are running. Therefore, power supply current can be calculated with the following formula: to be determined.
5
CY2278A
Switching Characteristics[8]
Parameter
t1 t2 t2
Output
All XCPUCLK CPUCLK, IOAPIC PCICLK USBCLK, CLK8MHZ REF0 REF1 XCPUCLK CPUCLK IOAPIC PCICLK USBCLK, CLK8MHZ XCPUCLK CPUCLK, IOAPIC PCICLK USBCLK, CLK8MHZ XCPUCLK, CPUCLK PCICLK XCPUCLK, PCICLK XCPUCLK, PCICLK XCPUCLK, CPUCLK XCPUCLK, CPUCLK USBCLK, PCICLK CLK8MHZ XCPUCLK, PCICLK, CPUCLK
Description
Output Duty Cycle[9] XCPU Clock Rising and Falling Edge Rate CPU and IOAPIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate
Test Conditions
t1 = t1A / t1B Between 0.4V and 2.0V for 2.5V clocks Between 0.4V and 2.0V for 2.5V clocks Between 0.4V and 2.4V for 3.3V clocks Between 0.4V and 2.4V
Min.
45 0.6 0.8
Typ.
50
Max.
55 4.0 4.0
Unit
% V/ns V/ns
t2 t2 t2 t2 t3 t3 t3 t3 t4 t4 t4 t4 t5 t5 t6
0.75 0.8 0.6 0.5 0.4 0.5 0.4 0.5
4.0 4.0 4.0 2.0 2.67 2.5 2.0 2.67 2.5
V/ns V/ns V/ns V/ns ns ns ns ns ns ns ns ns ps ps ps
USB, CLK8MHZ Clock Ris- Between 0.4V and 2.4V ing and Falling Edge Rate REF0 Clock Rising and Falling Edge Rate REF1 Rising and Falling Edge Rate XCPU Clock Rise Time CPU and IOAPIC Clock Rise Time PCI Clock Rise Time USB Clock and CLK8MHZ Rise Time XCPU Clock Fall Time CPU and IOAPIC Clock Fall Time PCI Clock Fall Time USB Clock and I/O Clock Fall Time XCPU-XCPU Clock Skew CPU-CPU Clock Skew PCI-PCI Clock Skew XCPU-PCI Clock Skew Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.0V Between 0.4V and 2.4V for 3.3V clocks Between 0.4V and 2.0V for 2.5V clocks Between 0.4V and 2.4V Between 0.4V and 2.4V Between 2.0V and 0.4V Between 2.4V and 0.4V for 3.3V clocks Between 2.0V and 0.4V for 2.5V clocks Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at 1.25V for 2.5V clocks Measured at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks (-1L, -2L, -4L configurations) Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks (-3L configuration) Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks
0.4 0.5 0.4 0.5
2.67 2.5 2.0 2.67 2.5 300 250 500 500
100
t6 t7 t8 t8 t8 t9
XCPU-PCI Clock Skew CPU-XCPU Clock Skew
1
3
5 750 400 500 650 3
ns ps ps ps ps ms
Cycle-Cycle Clock Jitter[10] Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time Measured at 1.5V Measured at 1.5V CPU, PCI clock stabilization from power-up
Notes:
8. All parameters specified with loaded outputs;SEL[2:0]=110. 9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V. 10. Room Temperature.
6
CY2278A
Switching Waveforms
Duty Cycle Timing
t1B
t1A OUTPUT
All Outputs Rise/Fall Time
VDD OUTPUT 0V t2 t3 t2 t4
XCPU-CPU Clock Skew
XCPUCLK-CPUCLK
t5
XCPU-PCI Clock Skew
XCPUCLK
PCICLK t6, t7
7
CY2278A
Switching Waveforms (continued)
CPU_RUN Timing[11, 12]
CPUCLK/ XCPUCLK (Internal) XCPUCLK_F (Free-Running) PCICLK (Internal) PCICLK (Free-Running) CPU_RUN CPUCLK (External)
PCI_RUN Timing[13, 14]
PCICLK (Internal) PCICLK (Free-Running) PCI_RUN PCICLK (External)
USB_RUN Timing[15]
USBCLK (Internal)
USB_RUN USBCLK (External)
PWR_DWN Timing
CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Notes: 11. CPUCLK on and CPUCLK off latency is 2 or 3 external CPUCLK cycles. 12. CPU_RUN may be applied asynchronously. It is synchronized internally. 13. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 14. PCI_RUN may be applied asynchronously. It is synchronized internally. 15. USBCLK on and USBCLK off latency is 2 USBCLK cycles.
8
CY2278A
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
Application Circuit
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > R trace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F- 22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
9
CY2278A
Test Circuit
VDDQ3
3
48 0.1 F 45
VDDQ2
6 0.1 F 9 42 39 36 14 0.1 F 33 16 30 26 0.1 F 25 0.1 F VDDCPU
0.1 F
0.1 F
19
22 0.1 F
OUTPUTS CLOAD
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Ordering Code CY2278APAC-1L CY2278APAC-2L CY2278APAC-3L CY2278APAC-4L Document #: 38-00619-D Package Name Z48 Z48 Z48 Z48 Package Type 48-Pin TSSOP 48-Pin TSSOP 48-Pin TSSOP 48-Pin TSSOP Operating Range Commercial Commercial Commercial Commercial
10
CY2278A
Package Diagram
48-Lead Thin Shrunk Small Outline Package Z48
51-85059-A
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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